This invention relates in general to sense amplifier circuits and in particular, to a sense amplifier circuit including a latch, and a pull-up circuit for accelerated latching of logic level output data.
FIG. 1 illustrates, as an example, a block diagram of a prior art circuit 1 which includes a conventional sense amplifier circuit 2 for sensing a voltage differential between two input signals, din1 and din2, and generating two output signals, dout1' and dout2', indicative of the sensed voltage differential. The sense amplifier circuit 2, being an analog circuit, typically does not generate its two output voltages, dout1' and dout2', at conventional logic level voltages, e.g., 5 volts (representing a logic level HIGH) and 0volts (representing a logic level LOW). Accordingly, the prior art circuit 1 also includes a conventional level shifting circuit 3 which receives the outputs, dout1' and dout2' , of the sense amplifier circuit 2, and converts or amplifies their respective signals such that corresponding outputs, dout1 and dout2, of the level shifting circuit 3 not only are indicative of the voltage differential sensed by the sense amplifier circuit 2, but also are generated at appropriate logic level voltages for digital processing purposes. Finally, the prior art circuit 1 also includes a latch 4 for latching the outputs, dout1 and dout2, of the level shifting circuit 3.